As electronic devices utilizing wireless digital communications techniques become increasingly prevalent in modern society, the increase in wireless traffic over a fixed number of allocated frequency bands forces product designers to maximize efficient allocation and use of the frequency spectrum.
To achieve more efficient utilization of a limited frequency spectrum and increased performance of radio traffic on adjacent channels, designers frequently employ techniques which involve filtering of the signal at various stages in the transmission process. However, while filtering the digital signal at the transmitter side of a communications link improves certain characteristics of the transmitted signal, this practice places additional burden on the receiver. Specifically, the digital signal recovered by the receiver demodulator typically is not a clean digital signalxe2x80x94rather, it tends to be sinusoidal in nature. In order to interface the recovered signal with digital receiver circuitry, it is necessary to employ a circuit known as a data slicer to square up the received signal into a format compatible with standard digital logic.
One type of data slicer known in the art consists primarily of a comparator, which compares the recovered signal with a reference level. Such prior art data slicers then effectively square up the input signal by transitioning their output between logic high and logic low levels as the input signal crosses the reference level.
However, one disadvantage with many prior art data slicers is that extended sequences of ones or zeros in the recovered data stream output from the receiver demodulator can cause erroneous output from the data slicer. These quasi-DC data segments can cause the reference level to begin drifting, or a coupling capacitor to begin accumulating a significant charge, thereby degrading the accuracy of the signal presented to the comparator in the data slicer. Such effects increase the probability of error being introduced in the demodulated data. Accordingly, it is an object of the present invention to prevent the introduction of errors due to data slicer reference level drift.
Certain prior art data slicer designs require each received transmission to begin with a predetermined preamble bit sequence in order for the data slicer to acquire the proper reference level. However, such preamble bits either reduce the usable channel data rate, or increase the channel frequency bandwidth. Therefore, it is an object of this invention to operate without requiring a preamble bit sequence.
Many modern communications systems incorporate time division duplexing or time division multiplexing wherein transmit and receive data from one or more devices is communicated via separate timeslots of a given frequency channel. In such systems, the receiver demodulator will send out valid data on an intermittent basis. Accordingly, it is an object of the present invention to prevent the reference level from changing between periods during which valid data is received.
Frequency hopping communications techniques are increasingly popular in modern communications systems due to their improved power efficiency, security, and resistance to interference. However, varying channel characteristics may result in differing nominal DC levels in the demodulator output for each channel. Therefore, each channel may have a unique ideal reference level for the data slicer comparator. Accordingly, it is an object of this invention to store separate data slicer reference levels for each channel of a multi-channel receiver.
Communications channel interference, and other effects can cause the received data to contain errors. A data slicer reference value derived from an error-ridden packet of received data may also be erroneous. Accordingly, it is an object of this invention for the data slicer to only update channel reference values only when the data received is error-free.
These and other objects of the present invention will become apparent in view of the present specification and drawings.
The invention includes a data slicer, and a method for slicing data. The data slicer compares an input signal to a reference level, outputting a logic high level when the input signal level is greater than the reference level, and a logic low level when the input signal level is below the reference level.
The data slicer generates a reference level based upon the input signal. The reference level can be determined by applying the input signal to a lowpass filter. After input data has been applied to the filter for a predetermined time period, the reference level is sampled by a signal level measurement circuit, which may include an analog-to-digital converter. The reference level is thereafter held constant at a desired level for the remainder of the received data frame. The desired level may be the measured level. Optionally, the desired level may be equal to a lower limit if the measured level is below the lower limit, or the desired level may be equal to an upper limit if the measured level is above the upper limit. The reference level may be determined by the state of a signal generator, which may include a digital-to-analog converter, that is connected to the comparator by a switch changing from an open to a closed position.
The measured reference level is stored so that the filter can be set to it as an initial condition at the start of subsequent transmissions on the given channel. Optionally, the reference level might only be stored if the data for which it was used to receive contained no errors. The reference levels might be stored by a controller, which controller would also control the analog-to-digital and digital-to-analog converters, and the state of the switch. The controller may store an independent reference level for each channel of a multi-channel receiver.